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HCF40162B
SYNCHRONOUS PROGRAMMABLE 4-BIT DECADE COUNTER WITH SYNCHRONOUS CLEAR
s
s s s s
s s s
s s
INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF40162BEY HCF40162BM1 T&R HCF40162M013TR
DESCRIPTION HCF40162B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40162B is a 4-bit synchronous programmable counter. The CLEAR function is synchronous. A low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. A low level at the LOAD inputs disables the counter and causes the output to agree with the set-up data after the following CLOCK pulse regardless of the condition of the ENABLE inputs. The carry
look-ahead circuitry provides for cascading counter for n-bit synchronous application without additional gating. Counting is enabled when both the PE and TE inputs are high. The TE input is fed forward to enable COUT. This enable output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE and TE inputs may occur when the clock is either high or low.
PIN CONNECTION
September 2002
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HCF40162B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2 3, 4, 5, 6 7 10 9 14, 13, 12, 11 15 8 16 SYMBOL CLEAR CLOCK P1 to P4 PE TE LOAD Q1 to Q4 NAME AND FUNCTION Synchronous Master Reset Clock Input (LOW to HIGH, Edge-triggered) Data Inputs Count Enable Input Count Enable Carry Input Parallel Enable Input Flip Flop Outputs
CARRY OUT Terminal Count Output VSS Negative Supply Voltage VDD Positive Supply Voltage
LOGIC DIAGRAM
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TRUTH TABLE
CLOCK CLR H H H H L H
(X) : Don't Care NC : No Change
LOAD L H H H X X
PE X L X H X X
TE X X L H X X
OPERATION PRESET NC NC COUNT X X
TIMING DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 200 80 60 225 95 70 125 55 40 120 45 30 120 45 30 170 70 50 Max. 400 160 120 450 190 140 250 110 80 ns Unit
tPLH tPHL Propagation Delay Time Clock to Q tPLH tPHL Propagation Delay Time Clock to COUT tPLH tPHL Propagation Delay Time TE to COUT tsetup Setup Time Data to Clock tsetup Setup Time Load to Clock tsetup Setup Time PE or TE to Clock thold Hold Time
ns
ns
240 90 60 240 90 60 340 140 100 0 0 0
ns
ns
ns
ns 100 50 40 85 35 25 3 8.5 12 200 100 80
tTHL tTLH Transition Time
ns
tW
Clock Input Pulse Width
fCL
Maximum Clock Input Frequency Clock Input Rise or Fall Time Proagation Delay Time Clear to Clock Hold Time Clear to Clock
170 70 50 2 5.5 8
ns
MHz 200 70 15
tr tf
ns
tSETUP
thold
trem
Clear Removal Time
340 140 100 0 0 0 200 100 70
170 70 50
ns
ns 100 50 35
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
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TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1 : PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
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WAVEFORM 2 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 4 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
WAVEFORM 5 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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TYPICAL APPLICATION: DETAIL OF FLIP-FLOPS (Asynchronous Clear)
TYPICAL APPLICATION: CASCADING COUNTER PACKAGES IN THE PARALLEL-CLOCKED MODE
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TYPICAL APPLICATION: CASCADING COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE
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HCF40162B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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